BAR Address Map

PCIe Topology describes which physical functions a SLASH board exposes. This page describes what is behind each BAR — the host-visible offset of every register block, and the device-side resource it reaches.

All three functions are generated by a single CPM5 controller instance configured as CPM_PCIE1 in QDMA mode (Gen5 x8). Two things determine the map:

BAR sizes and BAR-to-AXI translation — the CPM_PCIE1_PF*_BAR*_QDMA_* and CPM_PCIE1_PF*_PCIEBAR2AXIBAR_QDMA_* parameters on the CIPS block.
What answers at each AXI address — the address segments assigned to the cips/CPM_PCIE_NOC_0 and CPM_PCIE_NOC_1 master address spaces.

Both live in the shell block design script, top.tcl, for the compute and service shells respectively.

BAR Summary

PF	Device ID	Driver	BAR	Size / type	Device AXI base
PF0	`0x50B4`	`ami`	BAR0	256 MB, prefetchable, AXI Bridge Master	`0x0000_0201_0000_0000`
PF1	`0x50C1`	`slash_qdma`	BAR0	512 KB, prefetchable, DMA	(QDMA register space — not translated)
PF2	`0x50C2`	`slash_ctl`	BAR0	128 MB, AXI Bridge Master	`0x0000_0202_0000_0000`
PF2	`0x50C2`	`slash_ctl`	BAR2	128 MB, AXI Bridge Master	`0x0000_0203_0000_0000`
PF2	`0x50C2`	`slash_ctl`	BAR4	128 MB, prefetchable, AXI Bridge Master	`0x0000_0204_0000_0000`

Every BAR is 64-bit, so BAR1, BAR3, and BAR5 are the upper halves of the preceding BAR and report a size of zero in lspci. PF0 BAR2, PF1 BAR2, and PF2 BAR3 are declared in the CIPS configuration but left disabled.

Because the translation bases are 4 GB-aligned and every window is a power of two no larger than 256 MB, the host-side offset of any block is simply its device AXI address modulo the BAR length. VRT relies on exactly this identity when it converts a system_map.xml base address into a BAR offset.

PF0 BAR0 — Management

256 MB window onto 0x0000_0201_0000_0000. Owned by the AVED ami driver; SLASH does not access it directly.

BAR offset	Size	Device-side resource
`0x0010_0000`	—	hw_discovery BAR layout table (three slots). Enumerates the entries below to the management driver.
`0x0100_0000`	4 KB	`hw_discovery/s_axi_ctrl_pf0` control registers.
`0x0100_1000`	4 KB	`base_logic/uuid_rom` — logic UUID. Discovery entry type `0x50`.
`0x0101_0000`	4 KB	`base_logic/gcq_m2r` — GCQ mailbox to the RPU. Entry type `0x54`.
`0x0104_0000`	4 KB	`clock_reset/pcie_mgmt_pdi_reset` AXI GPIO.
`0x0800_0000`	128 MB	Discovery entry type `0x55`. See the note below.

The discovery table’s C_PF0_ENTRY_ADDR_* values are BAR-relative offsets and match the assigned AXI addresses exactly.

Note

The 128 MB entry at 0x0800_0000 maps a DDR window in the AVED reference block design. The SLASH shells deliberately drop it: both top.tcl scripts call exclude_bd_addr_seg on C0_DDR_LOW0 for the CPM_PCIE_NOC_0 address space, so the aperture is still advertised in the discovery table but nothing decodes it.

PF1 BAR0 — QDMA

512 KB, declared with BAR0_QDMA_TYPE {DMA}. Unlike every other BAR in the design this is not an address-translated window into the NoC — it is the QDMA IP’s own register file: queue contexts, doorbells, and per-queue control. The MSI-X table is configured at offset 0x0005_0000 with 8 entries.

The DMA engine’s device-side reach is the CPM master address space described under Device Memory Behind the DMA Path, not this BAR.

PF2 BAR0 — User Region

128 MB window onto 0x0000_0202_0000_0000. This is the BAR VRT opens for kernel register access; vrt::Device defaults to BAR index 0.

BAR offset	Size	Device-side resource
`0x0000_0000` onwards	per kernel	User kernel AXI-Lite control apertures.
`0x0060_0000`	2 MB	`axi_dbg_hub_0` AXI Debug Hub. Fixed address; present only when the design declares debug nets.

Kernel apertures are bump-allocated by the linker from the base of the window, in sorted instance-name order, each aligned to the larger of 256 bytes and the kernel’s own register-block range — in practice one 64 KB slot per instance. The allocation is deterministic but depends on which kernels were linked, so the authoritative list for a given .vbin is the host-view base address recorded for each kernel in its system_map.xml.

The RP1 command processor sees the same apertures through its own address window:

r5_addr = xml_addr - 0x0202_0000_0000 + 0x8800_0000

PF2 BAR2 — Service Layer

128 MB window onto 0x0000_0203_0000_0000. Unused by the compute shell. In the service shell:

BAR offset	Size	Device-side resource
`0x0000_0000` – `0x0007_0000`	64 KB each	`service_layer/eth_0` … `eth_7` control interfaces.
`0x0009_0000` – `0x000F_0000`	64 KB each	Service-layer traffic producers, in shells that instantiate them.
`0x0200_0000`	256 KB	`qsfp_0_n_1` DCMAC 0 (`dcmac_wrapper/dcmac_0/s_axi`).
`0x0300_0000`	256 KB	`qsfp_2_n_3` DCMAC 1 (`dcmac_wrapper/dcmac_1/s_axi`).

PF2 BAR4 — Static Shell

128 MB window onto 0x0000_0204_0000_0000. Present in both shells.

BAR offset	Size	Device-side resource
`0x0000_0000`	64 KB	`clk_rst_shell/clk_wizard_slash` — user-region clock.
`0x0001_0000`	64 KB	`clk_rst_shell/clk_wizard_service` — service-layer clock.
`0x0002_0000`	64 KB	`clk_rst_shell/build_id_gpio` — shell build ID.
`0x0400_0000`	64 MB	RP1 host-shared DDR window. See the note below.

The build-ID GPIO carries the shell provenance that v80-smi reports: channel 1 (+0x0) holds the low 32 bits of the commit prefix, and channel 2 (+0x8) packs the remaining hash in bits [27:0], the shell variant in bit [28], and a dirty-tree flag in bit [31].

Note

The RP1 window corresponds to RP1 physical address 0x3000_0000 and is the aperture used by Rp1BarWindow in the VRT graph backend and by v80-smi debug rp1-dump / rp1-ping (whose defaults are --bar 4 --ctrl-offset 0x4000000). It is a host-side convention: the compute and service top.tcl scripts in this repository do not currently assign an address segment at 0x0204_0400_0000, so the window resolves only on shells that add one.

Device Memory Behind the DMA Path

Buffers do not live behind any BAR. Descriptors submitted to the QDMA engine carry device AXI addresses, which the CPM master ports decode as follows.

Device AXI	Size	Resource	Ports
`0x00_0000_0000`	2 GB	DDR4 `C1_DDR_LOW0`	`CPM_PCIE_NOC_1` only
`0x01_0122_0000`	64 KB	PMC slave boot — PDI download path	both
`0x01_0210_0000`	64 KB	PMC slave boot stream	both
`0x40_0000_0000`	32 GB	HBM — `HBM0_PC0` … `HBM15_PC1`, 1 GB per pseudo-channel	both
`0x50_0080_0000`	2 GB	DDR4 `C1_DDR_CH1`	`CPM_PCIE_NOC_1` only
`0x60_0000_0000`	32 GB	DDR4 channel 2 — `C0_DDR_CH2` from port 0, `C1_DDR_CH2` from port 1	both

CPM_PCIE_NOC_0 reaches HBM and the 32 GB DDR4 channel only: the shell excludes C0_DDR_LOW0 and C0_DDR_CH1 from that address space. CPM_PCIE_NOC_1 additionally sees the two 2 GB low DDR windows.

The pseudo-channel names above are the NoC’s view of the HBM stacks. They are distinct from the HBM0–HBM63 port numbering that VRT and the linker sp= directives use; see Memory Model.

In the opposite direction, the bridge exposes six 1 GB device-to-host windows spanning device AXI 0x80_0000_0000 through 0x81_7FFF_FFFF (CPM_PCIE1_PF0_AXIBAR2PCIE_BASEADDR_0 … _5), which is how card-side masters reach host memory.