SLASH: An Open-Source Research Shell for Alveo V80

SLASH is an open-source platform for AMD Alveo V80 FPGA boards. It provides a complete runtime and development ecosystem for FPGA kernel execution, device management, and memory operations.

Tutorials

• Getting Started
  • Prerequisites
  • What the Example Does
  • Build the Example
  • Run the Example
  • Understanding the Code
  • Next Steps
• Your First Kernel
  • Prerequisites
  • Anatomy of an HLS Kernel
  • HLS Configuration File
  • Linker Configuration
  • CMake Build Setup
  • Build and Run
  • Creating Your Own Project
  • Next Steps
• Buffers and Memory
  • Memory Types on the V80
  • Creating Buffers
  • Host-Device Data Transfer
  • Accessing Buffer Data
  • Complete Example
  • Common Patterns
  • Next Steps
• Emulation and Simulation
  • Prerequisites
  • When to Use Each Mode
  • Build an Emulation Vrtbin
  • Run in Emulation
  • Build and Run in Simulation
  • Querying the Platform at Runtime
  • How Buffers Work in Emulation and Simulation
  • Known Limitations
  • Next Steps
• Using the Graph API
  • Author a CPU Pipeline
  • Compile and Run
  • Structured Control
  • FPGA Images
• Bring Up a V80 Board
  • Prerequisites
  • Verify the Kernel Module
  • Verify the Daemon
  • User Access
  • Program the Board
  • Validate the Board
  • Next Steps
• Bootstrapping with AVED
  • When you need this tutorial
  • Prerequisites
  • Download the AVED Deployment Archive
  • Switch the V80 to JTAG Boot Mode
  • Program OSPI Flash via Vivado Hardware Manager
  • Cold-Reboot the Host
  • Verify
  • Next Steps
• Device Management
  • Prerequisites
  • Listing Devices
  • Inspecting a Vrtbin
  • Programming a Device
  • Querying the Active Design
  • Resetting a Device
  • Validating Memory
  • Next Steps
• vrtd Configuration
  • Prerequisites
  • How vrtd Manages Access
  • Configuration File
  • Understanding Roles
  • User and Group Mappings
  • Creating a Custom Role
  • Per-Device Permissions
  • Systemd Integration
  • Multi-Tenancy
  • Troubleshooting
  • Next Steps

How-To Guides

• How-To Guides
  • Build and Install SLASH
  • Use Multiple Boards
  • Set Clock Frequency
  • Chain Streaming Kernels
  • Use DCMAC (Ethernet Loopback)
  • Benchmark Memory
  • Offload Builds to a Cluster
  • Use CMake Modules
  • Inspect vrtbin Metadata
  • Debug Graphs with DOT
  • Use Mock Mode
  • Migrate from XRT to VRT
  • Using RTL Kernels
  • Debugging Kernels with ILA Debug Cores

Reference

• VRT C++ API
  • vrt::Device
  • vrt::Kernel
  • vrt::Buffer
  • vrt::StreamingBuffer
  • vrt::Vrtbin
  • VRT Enumerations
  • vrt::graph API
  • Graph Devices
  • Graph DOT Rendering
• libslash C API
  • Control Device (ctldev)
  • QDMA
  • Hotplug
• Kernel ABI
  • Data Conventions
  • Concurrency Model
  • Card information and BARs: /dev/slash_ctl<N>
  • Memory transfers via QDMA: /dev/slash_qdma_ctl<N>
  • Device resets and hotplugging: /dev/slash_hotplug
• libvrtd C Client API
  • vrtd Client Functions
  • Wire Protocol
• libvrtdpp C++ Client API
  • vrtd::Session
  • vrtd::Device
  • vrtd::Bar
  • vrtd::BarFile
  • vrtd::Buffer
  • vrtd::QdmaQpair
• vrtd Daemon
  • Client Flow
  • Configuration
• FPGA Model ZMQ Protocol
  • Transport and Framing
  • The two dialects
  • Command Reference
  • Naming conventions
  • VBIN metadata
• v80-smi
  • Command Reference
• CMake Modules
  • SlashTools
  • BuildHLS
  • FindVivado and FindVitis

Explanation

• Architecture
  • Stack Overview
  • Layer Descriptions
  • Typical Execution Flow
• Graph API Architecture
  • Compilation Pipeline
  • Direct Backend Lowering
  • Cross-Device Transfers
  • FPGA Control
  • Failure Model
• Memory Model
  • DDR Memory
  • HBM (High Bandwidth Memory)
  • MemoryConfig and Port Mapping
  • Graph Buffers Across HBM Banks
  • Buddy Allocator
  • Platform Differences
• SLASH Networking
  • The DCMAC
  • DCMAC integration in SLASH
  • Source Code
  • See Also
• vrtbin Format
  • Overview
  • Archive Contents
  • system_map.xml
  • How VRT Uses the Vrtbin
  • Graph API and RP1
  • Inspecting a Vrtbin
  • Creating a Vrtbin
• PCIe Topology
  • Physical Functions
  • BDF Addressing
  • Device Discovery
  • Readiness Checks
  • Hotplug Lifecycle
  • Segmented Configuration
  • See Also
• BAR Address Map
  • BAR Summary
  • PF0 BAR0 — Management
  • PF1 BAR0 — QDMA
  • PF2 BAR0 — User Region
  • PF2 BAR2 — Service Layer
  • PF2 BAR4 — Static Shell
  • Device Memory Behind the DMA Path
  • See Also
• Platform Modes
  • Platform Selection
  • Building for Each Platform
  • Hardware
  • Emulation
  • Simulation
• System Emulation
  • Usage
  • Implementation

Examples

• Examples